-A A +A
We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20× 20 nm 2 is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.
IOP Publishing
Publication date: 
3 May 2012

Enrico Prati, Marco De Michielis, Matteo Belli, Simone Cocco, Marco Fanciulli, Dharmraj Kotekar-Patil, Matthias Ruoff, Dieter P Kern, David A Wharam, Jan Verduijn, Giuseppe C Tettamanzi, Sven Rogge, Benoit Roche, Romain Wacquez, Xavier Jehl, Maud Vinet, Marc Sanquer

Biblio References: 
Volume: 23 Issue: 21 Pages: 215204